5CSEBA2U19A7N vs 5CSEBA2U19C6N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA2U19A7N sa pamamagitan ng Altera at 5CSEBA2U19C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro 5CSEBA2U19A7N 5CSEBA2U19C6N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Aktibo
Family Cyclone V SE SoC FPGA Cyclone V SE SoC FPGA
Device Variant 5CSEA2 (U19 device) —
Logic Elements 25,000 25 K
Process Technology 28 nm low-power TSMC 28 nm low-power
HPS Processor Dual ARM Cortex-A9 MPCore with CoreSight —
HPS Maximum Frequency 700 MHz —
Core Voltage (VCCINT) 1.1 V —
Temperature Grade Automotive A7 —
AEC-Q100 Qualified —
Packhaging 484-UBGA (U19), 19x19 mm 484-pin UBGA (19x19 mm)
Uri ng Pagpapasok Surface Mount (FBGA) Surface Mount
User I/O Pins 161 —
Memory Embedded SRAM + DDR3/LPDDR2 controller (HPS) —
DSP Blocks Variable-precision, embedded multiplier/accumulator Variable-precision DSP
Tindminan RoHS Compliant Compliant
Level ng MSL [DATA_NEEDED: MSL level] —
Lead-Free Yes —
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Clock Frequency — 925 MHz
Operating Temperature Grade — Commercial (other)
Memory Interfaces — DDR2, DDR3, LPDDR2 with ECC
HPS Peripherals — GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC
L2 Cache — 512 KB shared
L1 Cache per Core — 32 KB I-cache + 32 KB D-cache
FPGA-to-HPS Bridges — AXI-32/AXI-64, FPGA-to-SDRAM ports

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