5CSEBA2U19C7SN vs 5CSEBA2U19A7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA2U19C7SN sa pamamagitan ng Altera at 5CSEBA2U19A7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
5CSEBA2U19A7N - Cyclone V SE SoC FPGA 25K LE, A7 Automotive | Altera
5CSEBA2U19A7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA2U19C7SN | 5CSEBA2U19A7N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE FPGA SoC | Cyclone V SE SoC FPGA |
| Device Variant | 5CSEA2 (single-core ARM Cortex-A9) | 5CSEA2 (U19 device) |
| Logic Elements | 25,000 | 25,000 |
| Processor Hard Core | Single ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Processor Frequency | 800 MHz | — |
| User I/O Count | 161 (5CSEBA2 variant) | — |
| Packhaging | 484-UBGA (19x19 mm) | 484-UBGA (U19), 19x19 mm |
| Speed Grade | C7 (commercial) | — |
| Temperature na Operasyon | 0C to +85C (commercial, C7 suffix) | — |
| Process Technology | TSMC 28 nm low-power | 28 nm low-power |
| Memory Blocks | M10K + MLAB embedded RAM | — |
| DSP Blocks | Variable-precision DSP | Variable-precision, embedded multiplier/accumulator |
| HPS Memory Controller | DDR2, DDR3, LPDDR2, LPDDR | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (FBGA) |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| HPS Processor | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 700 MHz |
| Core Voltage (VCCINT) | — | 1.1 V |
| Temperature Grade | — | Automotive A7 |
| AEC-Q100 | — | Qualified |
| User I/O Pins | — | 161 |
| Memory | — | Embedded SRAM + DDR3/LPDDR2 controller (HPS) |
| Lead-Free | — | Yes |