5CSEBA4U19C8N vs 5CSEBA5U19C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA4U19C8N sa pamamagitan ng Intel at 5CSEBA5U19C8N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA4U19C8N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C8N ✓ NakahandaIntel
5CSEBA5U19C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C8N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA4U19C8N | 5CSEBA5U19C8N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE (SoC FPGA) |
| Logic Elements | 40K | 85,000 LE |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 600 MHz | — |
| FPGA Fabric Speed Grade | -8 | — |
| Packhaging | 484-UBGA (19x19 mm) | 484-UBGA (U19, 19x19 mm) |
| Temperature na Operasyon | 0C to +85C (commercial) | 0C to +85C (commercial) |
| Process Technology | TSMC 28nm low-power | 28 nm TSMC |
| User I/O Count | 161 | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (SMD/SMT) |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Level ng MSL | 3 (168 hours) | — |
| Supply Voltage (Core) | [DATA_NEEDED: VCC core voltage] | — |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks] | — |
| Embedded Memory (M10K) | [DATA_NEEDED: M10K block count] | — |
| Transceivers | None (SE variant - no high-speed transceivers) | — |
| Configuration Method | Serial (EPCS) and Parallel | — |
| Adaptive Logic Modules (ALMs) | — | 32,070 ALM |
| Embedded Memory | — | 3.88 Mbit |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Core Maximum Frequency | — | 925 MHz (datasheet); 600 MHz commercial speed grade |
| L1 Cache (Instruction) | — | 2 x 32 kB |
| L1 Cache (Data) | — | 2 x 32 kB |
| L2 Cache | — | 512 kB shared |
| FPGA User I/Os | — | 66 I/O |
| Core Voltage | — | 1.1 V |
| Ball Pitch | — | [DATA_NEEDED: ball pitch in mm] |
| Speed Grade | — | C8 (0.85 ns, commercial) |