5CSEBA4U19I7N vs 5CSEBA4U19I7SN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA4U19I7N sa pamamagitan ng Altera at 5CSEBA4U19I7SN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA4U19I7SN - Cyclone V SE SoC FPGA, 40K LE, ARM Cortex-A9 | Intel
5CSEBA4U19I7SN ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA4U19I7N | 5CSEBA4U19I7SN |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | — |
| Logic Elements | 40 K | 40,000 |
| Processor | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz | 800 MHz |
| Packhaging | 484-UBGA (19x19 mm) | 484-pin UBG A (19x19 mm) |
| User I/O Pins | 240 | — |
| Operating Temperature Grade | Industrial (-40C to +100C) | — |
| Process Technology | 28 nm low-power | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| HPS Peripherals | USB 2.0, EMAC, NAND flash controller, DDR3 controller | — |
| I/O Standards | LVDS, LVTTL, LVCMOS | — |
| Speed Grade | I7 (industrial) | — |
| Series | — | Cyclone V SE SoC FPGA |
| Device Family | — | Cyclone V |
| Hard Processor System (HPS) | — | Single ARM Cortex-A9 MPCore with CoreSight |
| Temperature na Operasyon | — | -40C to +100C (Industrial) |
| Process Node | — | 28 nm low-power |
| Supply Voltage (Core) | — | 1.1 V (typical) |
| I/O Standards Supported | — | LVTTL, LVCMOS, LVDS, SSTL, HSTL (Cyclone V I/O family) |
| Embedded Memory | — | [DATA_NEEDED: total Kbits of M9K blocks] |
| 18x18 Hardware Multipliers | — | [DATA_NEEDED: count] |
| PLLs | — | [DATA_NEEDED: count] |
| Transceivers | — | Not applicable (SE family, transceiver-less) |
| PCI Express Hard IP | — | Gen1 capable (rootport/endpoint) |
| DDR Memory Support | — | DDR2/DDR3/LPDDR2 via HPS and FPGA fabric |