5CSEBA4U23C7N vs 5CSEBA4U23I7LN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA4U23C7N sa pamamagitan ng Intel at 5CSEBA4U23I7LN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA4U23C7N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U23C7N ✓ NakahandaIntel
5CSEBA4U23I7LN - Cyclone V SE SoC FPGA 40K LE Dual A9 925MHz | Intel
5CSEBA4U23I7LN ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA4U23C7N | 5CSEBA4U23I7LN |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Device Variant | 5CSEA4 (Logic Element density) | — |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Logic Elements | 40,000 | 40,000 |
| HPS Maximum Core Frequency | 800 MHz | — |
| DSP Blocks (18x18) | 224 | — |
| Embedded Memory | Approximately 2.7 Mbits (M10K + M9K) | [DATA_NEEDED: exact embedded memory size in bits] |
| Packhaging | 672-ball UBGAs (UBGA), 23x23 mm | 672-pin UBGA (23x23 mm) |
| Core Voltage | 1.1 V | — |
| User I/O Count | 364 | — |
| High-Speed Transceivers | 6 (up to 3.125 Gbps) | — |
| PCIe Hard IP | 2 Gen2 blocks | — |
| Temperature na Operasyon | Commercial 0C to +85C (C7 speed grade) | -40C to +100C (Industrial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Process Technology | TSMC 28 nm low-power | 28nm TSMC low-power |
| HPS Memory Interface | DDR3, DDR3L, LPDDR2 (16-bit + ECC option) | — |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Processor Clock Speed | — | 925 MHz |
| DSP Blocks (18x18 multipliers) | — | [DATA_NEEDED: exact multiplier count] |
| Transceivers | — | 3.125 Gbps (per Cyclone V family) |
| External Memory Interface | — | DDR3, DDR2, LPDDR2 (controller integrated in HPS + soft IP in FPGA fabric) |
| Level ng MSL | — | 3 |
| Lead-Free | — | Yes |
| Wala sa Halogen | — | [DATA_NEEDED] |
| Number of GPIOs | — | [DATA_NEEDED: per device variant] |
| Number of PLLs | — | [DATA_NEEDED: per device variant] |