5CSEBA5U19C7N vs 5CSEBA5U19C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA5U19C7N sa pamamagitan ng Intel at 5CSEBA5U19C8N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19C7N - Cyclone V SE SoC FPGA 85K LE Dual A9 800MHz | Altera
5CSEBA5U19C7N ✓ NakahandaIntel
5CSEBA5U19C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C8N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA5U19C7N | 5CSEBA5U19C8N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE (SoC FPGA) |
| Logic Elements | 85,000 | 85,000 LE |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Maximum Frequency | 800 MHz per core | — |
| Packhaging | 484-UBGA (UBGAmobile, 19x19 mm) | 484-UBGA (U19, 19x19 mm) |
| Temperature na Operasyon | 0C to +85C (commercial, junction) | 0C to +85C (commercial) |
| Speed Grade | -7 (standard) | C8 (0.85 ns, commercial) |
| Process Node | 28 nm low-power (TSMC) | — |
| Supply Voltage (Core) | 1.1 V typical | — |
| DSP Blocks | Variable-precision, 18x18 / 27x27 multipliers | — |
| Embedded Memory | M10K + MLAB blocks, ~4,450 Kbits total | 3.88 Mbit |
| HPS Peripherals | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (SMD/SMT) |
| RoHS / Pb-free | Yes | — |
| Configuration Memory | External (active serial via HPS or FPGA) | — |
| Level ng MSL | 3 (per JEDEC J-STD-020, reflow 260C) | — |
| Block Pins (User I/O) | Approximately 66 user I/O pins | — |
| Adaptive Logic Modules (ALMs) | — | 32,070 ALM |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Core Maximum Frequency | — | 925 MHz (datasheet); 600 MHz commercial speed grade |
| L1 Cache (Instruction) | — | 2 x 32 kB |
| L1 Cache (Data) | — | 2 x 32 kB |
| L2 Cache | — | 512 kB shared |
| FPGA User I/Os | — | 66 I/O |
| Process Technology | — | 28 nm TSMC |
| Core Voltage | — | 1.1 V |
| Ball Pitch | — | [DATA_NEEDED: ball pitch in mm] |
| Tindminan RoHS | — | Compliant |