5CSXFC4C6U23I7LN vs 5CSXFC5C6U23I7LN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSXFC4C6U23I7LN sa pamamagitan ng Altera at 5CSXFC5C6U23I7LN sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
5CSXFC4C6U23I7LN - Cyclone V SX SoC FPGA 40K LE Dual ARM Cortex-A9 925MHz 672-UBGA | Altera
5CSXFC4C6U23I7LN ✓ NakahandaIntel
5CSXFC5C6U23I7LN - Cyclone V SX SoC FPGA, 85K LE, ARM Cortex-A9 | Intel
5CSXFC5C6U23I7LN ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSXFC4C6U23I7LN | 5CSXFC5C6U23I7LN |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SX SoC FPGA | — |
| Device Variant | 5CSXFC4 (U23 package code) | — |
| Logic Elements | 40,000 | 85 K |
| Processor Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Maximum Processor Clock | 925 MHz | — |
| Process Technology | 28 nm low-power | — |
| Packhaging | 672-ball UBGA (23x23 mm) | 672-UBGA (23x23 mm) |
| Temperature na Operasyon | -40C to +100C (Industrial) | -40C to +100C (industrial, I7) |
| Speed Grade | I7 | — |
| Embedded Memory | [DATA_NEEDED: total block RAM bits] | 4,450 Kbits |
| DSP Blocks | [DATA_NEEDED: variable-precision DSP count] | 224 (18x19 variable-precision multipliers) |
| Transceivers | Integrated high-speed transceivers (PCIe Gen2 capable) | 6 channels, up to 3.125 Gbps |
| User I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| Tindminan RoHS | Compliant | Compliant (LN suffix) |
| Lead-Free | Yes | — |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Series | — | Cyclone V SX |
| Device Type | — | SoC FPGA (FPGA + ARM Cortex-A9 HPS) |
| Hard Processor System | — | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 925 MHz |
| Maximum User I/O | — | 364 (excluding HPS-dedicated pins) |
| Hard Memory Controllers | — | 2 |
| Memory Interface Support | — | DDR3, DDR3L, LPDDR2 |
| Process Node | — | TSMC 28 nm low-power |
| Configuration | — | Serial (AS) or Parallel (FPP) flash, bitstream encryption supported |