5M160ZE64C5N vs 5M160ZE64I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZE64C5N sa pamamagitan ng Altera at 5M160ZE64I5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M160ZE64C5N | 5M160ZE64I5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX V | — |
| Device Family | MAX V (5M160Z) | MAX V |
| Logic Elements (LE) | 160 | — |
| Macrocells | 128 | 128 |
| User I/O Pins | 54 | — |
| Maximum Operating Frequency (fMAX) | 118.3 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 1.4 ns (per datasheet) | 7.5 ns |
| Configuration Memory | Non-volatile Flash | — |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | 4.0 Kbits |
| Packhaging | 64-pin EQFP (E64) with exposed pad | 64-pin EQFP (Exposed Pad) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0°C to +85°C (commercial) | -40C to +100C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / In-system | — |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 | — |
| Logic Elements (LEs) | — | 160 |
| Maximum User I/O Pins | — | 79 |
| Logic Array Blocks (LABs) | — | 4 |
| Supply Voltage - Core | — | 3.3 V or 2.5 V |
| I/O Bank Voltages | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Support | — | Yes (IEEE 1149.1, TMS/TDI/TDO/TCK) |
| Differential I/O | — | LVDS, RSDS, mini-LVDS, LVPECL (emulated) |
| Configuration | — | Non-volatile on-chip flash, instant-on |