5M160ZE64C5N vs 5M160ZM68A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZE64C5N sa pamamagitan ng Altera at 5M160ZM68A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M160ZE64C5N | 5M160ZM68A5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX V | — |
| Device Family | MAX V (5M160Z) | — |
| Logic Elements (LE) | 160 | — |
| Macrocells | 128 | 128 |
| User I/O Pins | 54 | — |
| Maximum Operating Frequency (fMAX) | 118.3 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 1.4 ns (per datasheet) | — |
| Configuration Memory | Non-volatile Flash | — |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| User Flash Memory | 8 Kbits | 8 Kbits |
| Packhaging | 64-pin EQFP (E64) with exposed pad | 68-ball FBGA (FineLine BGA), 0.5 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | 0°C to +85°C (commercial) | -40C to +125C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / In-system | IEEE Std 1149.1 JTAG BST |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 | — |
| Family | — | MAX V |
| Device Variant | — | 5M160Z (128 macrocells, 1.8 V, speed grade -7) |
| Logic Array Blocks (LABs) | — | 4 |
| User I/Os | — | 52 |
| Propagation Delay (tPD) | — | 14 ns |
| Standby Current (ICCSTBY) | — | 25 uA (typical) |
| Core Supply Voltage (VCCINT) | — | 1.8 V (1.71 V to 1.89 V) |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| JEDEC Package Code | — | S-PBGA-B68 |
| Automotive Qualification | — | AEC-Q100 |