5M160ZT100I5N vs 5M160ZT100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZT100I5N sa pamamagitan ng Intel at 5M160ZT100C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M160ZT100I5N | 5M160ZT100C5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | — |
| Series | 5M160Z | MAX V |
| Macro Cells | 128 | 128 |
| Logic Elements (LEs) | 160 | 160 |
| Number of I/O | 79 (max user I/Os) | — |
| Maximum Internal Frequency | 118.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Voltage (VCCIO) | 1.2 V to 3.3 V (multi-voltage LVCMOS/LVTTL) | 1.5 V to 3.3 V |
| User Flash Memory | 8 Kbits | — |
| Packhaging | 100-pin TQFP (T100) | TQFP-100 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40 °C to +100 °C (industrial) | 0 °C to +85 °C (commercial) |
| Programmability | In-system via JTAG (IEEE 1149.1) | — |
| Configuration Memory | Non-volatile (flash-backed EEPROM) | — |
| Tindminan RoHS | Compliant | Compliant |
| Device Family | — | MAX V CPLD |
| User I/Os | — | 79 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Operating Frequency | — | 152 MHz (typical, internal) |
| User Flash Memory (UFM) | — | 8 Kbits |
| Level ng MSL | — | 3 |
| Lead-Free | — | Yes |
| Programming Interface | — | JTAG (IEEE 1149.1) - in-system |