5M160ZT100I5N vs 5M80ZT100I5N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng 5M160ZT100I5N sa pamamagitan ng Intel at 5M80ZT100I5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro 5M160ZT100I5N 5M80ZT100I5N
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Aktibo
Family MAX V MAX V CPLD
Series 5M160Z —
Macro Cells 128 —
Logic Elements (LEs) 160 —
Number of I/O 79 (max user I/Os) —
Maximum Internal Frequency 118.3 MHz —
Pin-to-Pin Delay (tPD) 7.5 ns —
Core Voltage (VCCINT) 1.8 V —
I/O Voltage (VCCIO) 1.2 V to 3.3 V (multi-voltage LVCMOS/LVTTL) —
User Flash Memory 8 Kbits —
Packhaging 100-pin TQFP (T100) TQFP-100 (100 pins, 0.5 mm pitch)
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon -40 °C to +100 °C (industrial) —
Programmability In-system via JTAG (IEEE 1149.1) —
Configuration Memory Non-volatile (flash-backed EEPROM) Internal non-volatile flash (instant-on)
Tindminan RoHS Compliant Compliant
Logic Elements (LE) — 80
Macrocells (approx.) — 160
User I/O Pins — 64
Pin-to-Pin Logic Delay (tPD) — 7.5 ns
Core Supply Voltage (VCCINT) — 1.71 V to 1.89 V (1.8 V typical)
I/O Supply Voltage (VCCIO) — 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V
Operating Temperature (Industrial) — -40 °C to +100 °C
UFM (User Flash Memory) — Up to 8 Kbits user-accessible
JTAG / ISP — IEEE 1149.1 boundary-scan + in-system programming
Level ng MSL — MSL3 (per JEDEC J-STD-020)

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