5M40ZE64C4N vs 5M40ZE64A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M40ZE64C4N sa pamamagitan ng Intel at 5M40ZE64A5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M40ZE64C4N | 5M40ZE64A5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | — |
| Logic Elements (LE) | 32 | 40 |
| User Flash Memory | 4 Kbit | 4 Kbit |
| Pin-to-Pin Delay (tPD1) | 7.5 ns | — |
| Maximum Internal Frequency | 184 MHz | — |
| Number of I/O Pins | 30 (approx.) | — |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage | 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash-based CMOS | — |
| Configuration Memory | Non-volatile flash (internal) | — |
| Programmable Pull-up Resistors | Yes (per-pin, internal) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | — |
| Packhaging | EQFP-64 (Plastic Enhanced QFP, 64 pins) | EQFP-64 (E64, 10x10 mm, 0.5 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (per JEDEC J-STD-020) | 3 (168 hours) |
| Tindminan RoHS | Compliant | Compliant (Pb-free) |
| Series | — | MAX V |
| Device Family | — | MAX V (5M40Z) |
| Logic Array Blocks (LAB) | — | 2 (20 LEs each) |
| Maximum User I/O | — | 30 |
| Pin-to-Pin Delay (tPD) | — | 5 ns (commercial speed grade) |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.2 V to 3.3 V (4 banks) |
| Hanay ng Temperature na Operasyon | — | 0 C to +85 C (commercial) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Method | — | On-chip non-volatile flash (instant-on) |