5M40ZE64C4N vs 5M40ZE64A5N 比較
詳細並排比較 5M40ZE64C4N 由 Intel 與 5M40ZE64A5N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | 5M40ZE64C4N | 5M40ZE64A5N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX V | — |
| Logic Elements (LE) | 32 | 40 |
| User Flash Memory | 4 Kbit | 4 Kbit |
| Pin-to-Pin Delay (tPD1) | 7.5 ns | — |
| Maximum Internal Frequency | 184 MHz | — |
| Number of I/O Pins | 30 (approx.) | — |
| Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage | 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm flash-based CMOS | — |
| Configuration Memory | Non-volatile flash (internal) | — |
| Programmable Pull-up Resistors | Yes (per-pin, internal) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| 工作溫度 | 0 °C to +85 °C (commercial) | — |
| 封裝 | EQFP-64 (Plastic Enhanced QFP, 64 pins) | EQFP-64 (E64, 10x10 mm, 0.5 mm pitch) |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | 3 (per JEDEC J-STD-020) | 3 (168 hours) |
| RoHS 狀態 | Compliant | Compliant (Pb-free) |
| Series | — | MAX V |
| Device Family | — | MAX V (5M40Z) |
| Logic Array Blocks (LAB) | — | 2 (20 LEs each) |
| Maximum User I/O | — | 30 |
| Pin-to-Pin Delay (tPD) | — | 5 ns (commercial speed grade) |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 1.2 V to 3.3 V (4 banks) |
| 工作溫度範圍 | — | 0 C to +85 C (commercial) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Configuration Method | — | On-chip non-volatile flash (instant-on) |