5M80ZT100A5N vs 5M80ZT100C5N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng 5M80ZT100A5N sa pamamagitan ng Altera at 5M80ZT100C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro 5M80ZT100A5N 5M80ZT100C5N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Aktibo
Family MAX V —
Macro Cells 64 —
Logic Elements / LABs 8 Logic Array Blocks (LABs) —
Maximum User I/O 80 (in TQFP-100 package) —
Pin-to-Pin Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fMAX) 118.3 MHz —
Core Supply Voltage (VCCINT) 1.8 V —
I/O Bank Supply Voltage (VCCIO) 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage banks) —
User Flash Memory (UFM) 8 Kbits (typical for MAX V 64-macrocell device) —
Configuration Memory Non-volatile, on-chip flash Non-volatile Flash
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532) JTAG (IEEE 1149.1)
Temperature ng Junction na Operasyon -40 C to +125 C (automotive/industrial grade) —
Packhaging 100-pin TQFP (T100) —
Uri ng Pagpapasok Surface Mount Surface Mount
Level ng MSL 3 (per JEDEC J-STD-020) —
Tindminan RoHS Compliant Compliant
Automotive Qualification AEC-Q100 (A5N suffix) —
Supply Current (typical) [DATA_NEEDED: Icc typical] —
Global Clock Networks 4 —
Lead-Free / Halogen-Free Yes / Yes (per Altera lead-free roadmap) —
Manufacturer — Intel (formerly Altera)
Series — MAX V
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements — 80
Macrocells — 64
Pin-to-Pin Delay (tPD) — 7.5 ns
User I/Os — 79
User Flash Memory — 8 Kbits
Package Type — 100-pin TQFP (T100)
Temperature na Operasyon — 0C to +85C (commercial)
Core Voltage — 1.71 V to 1.89 V
I/O Voltage (VCCIO) — 1.2 V to 3.3 V LVCMOS/LVTTL
Lead-Free — Yes

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