5M80ZT100C4N vs 5M80ZT100I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M80ZT100C4N sa pamamagitan ng Intel at 5M80ZT100I5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 5M80ZT100C4N | 5M80ZT100I5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | MAX V CPLD |
| Logic Elements (LEs) | 80 | — |
| Macrocells | 64 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum User I/O Pins | 79 | — |
| Number of Global Clocks | 4 | — |
| User Flash Memory | 8 Kbit | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Packhaging | TQFP-100 (T100) | TQFP-100 (100 pins, 0.5 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (Commercial) | — |
| Process Technology | 0.18 µm flash CMOS | — |
| Configuration Method | Non-volatile flash (instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Tindminan RoHS | Compliant | Compliant |
| Logic Elements (LE) | — | 80 |
| Macrocells (approx.) | — | 160 |
| User I/O Pins | — | 64 |
| Pin-to-Pin Logic Delay (tPD) | — | 7.5 ns |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V (1.8 V typical) |
| I/O Supply Voltage (VCCIO) | — | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Operating Temperature (Industrial) | — | -40 °C to +100 °C |
| Configuration Memory | — | Internal non-volatile flash (instant-on) |
| UFM (User Flash Memory) | — | Up to 8 Kbits user-accessible |
| JTAG / ISP | — | IEEE 1149.1 boundary-scan + in-system programming |
| Level ng MSL | — | MSL3 (per JEDEC J-STD-020) |