74HC165D,653 vs 74HC165D,652 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 74HC165D,653 sa pamamagitan ng Nexperia at 74HC165D,652 sa pamamagitan ng Nexperia. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Nexperia
74HC165D,653 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,653 ✓ NakahandaNexperia
74HC165D,652 - 8-Bit Parallel-In/Serial-Out Shift Register | Nexperia
74HC165D,652 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 74HC165D,653 | 74HC165D,652 |
|---|---|---|
| Brand | Nexperia | Nexperia |
| Kategorya | Logic ICs | Logic ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Logic Type | Shift Register (Parallel-in/Serial-out) | Shift Register |
| Fungsi | Parallel or Serial to Serial | Parallel or Serial to Serial |
| Number of Elements | 1 | 1 |
| Number of Bits per Element | 8 | 8 |
| Type ng Output | Differential (Q7 and Q7-bar complementary outputs) | Differential (complementary Q7 and Q7-bar) |
| Supply Voltage (VCC) | 2 V to 6 V | 2 V to 6 V |
| Input Voltage | 0 V to VCC | — |
| Output Drive (IO) | ±5.2 mA | — |
| Propagation Delay (tpd) | 6 ns typical at VCC = 5 V, CL = 50 pF [DATA_NEEDED: explicit propagation delay value] | — |
| Temperature na Operasyon | -40 C to +125 C | -40 °C to +125 °C |
| Packhaging | 16-pin SOIC (SOT109-1) | 16-SOIC (SOT109-1), 0.154" (3.90 mm) width |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 1 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | Compliant | Compliant |
| JEDEC Compliance | JESD7A (per datasheet) | — |
| Pin Compatibility | LSTTL 74LS165 | — |
| Technology | High-speed Si-gate CMOS | — |
| Logic Family | — | 74HC (high-speed Si-gate CMOS) |
| Input Type | — | CMOS (HC); pin-compatible with TTL/LSTTL |
| Bilang ng Pins | — | 16 |
| Standard Compliance | — | JEDEC standard no. 7A |
| Pin Compatible With | — | Low-power Schottky TTL (LSTTL) |
| Parallel Load | — | Asynchronous via SH/LD-bar |
| Serial Data Input | — | DS (for daisy-chaining) |
| Clock Input | — | CP (rising-edge triggered) with clock inhibit (CE-bar) |