A3PE3000L-1PQ208 vs A3PE3000L-PQ208 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A3PE3000L-1PQ208 sa pamamagitan ng Microchip Technology at A3PE3000L-PQ208 sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A3PE3000L-1PQ208 - ProASIC3L Flash FPGA 208-PQFP | Microchip
A3PE3000L-1PQ208 ✓ NakahandaMicrochip Technology
A3PE3000L-PQ208 - 3M Gate Low-Power Flash FPGA | Microchip
A3PE3000L-PQ208 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A3PE3000L-1PQ208 | A3PE3000L-PQ208 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | ProASIC3L (Low Power Flash FPGA) | ProASIC3L (ProASIC3EL) |
| System Gates | 3M gates | 3,000,000 |
| Logic Elements | 35K LEs | — |
| User I/O | 147 | — |
| Core Voltage | 1.2 V | 1.2 V |
| Core Voltage Range | 1.2 V to 1.5 V | — |
| Process Technology | 130 nm flash | 130 nm, 7-layer metal (6 copper) CMOS |
| Characteristic Frequency | 892.86 MHz | — |
| Configuration Memory | On-chip nonvolatile flash (Instant On) | — |
| Low Power Feature | Flash*Freeze technology | — |
| Packhaging | 208-BFQFP (PQFP-208) | 208-BFQFP (PQ208), 1.0 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packaging | Tray | Tray |
| Level ng MSL | 3 (168 hours) | — |
| ECCN | 3A001A7A | — |
| HTSUS | 8542.39.0001 | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status for A3PE3000L-1PQ208] | RoHS Non-Compliant (contains lead) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C |
| Embedded SRAM | — | 504 kbits true dual-port |
| User I/Os (PQ208) | — | 147 |
| Volte ng Pagbibigay | — | 1.5 V |
| Maximum Frequency | — | 781.25 MHz |
| Logic Family | — | CMOS |
| Program Type | — | Flash-based, In-System Programmable |
| Power-Up Behavior | — | Live At Power-Up Level 0 |
| Configuration | — | Single-chip solution (no external boot device) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |