A42MX24-2PLG84I vs A42MX16-2PLG84 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A42MX24-2PLG84I sa pamamagitan ng Microchip Technology at A42MX16-2PLG84 sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A42MX24-2PLG84I | A42MX16-2PLG84 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MX (42MX) | 42MX FPGA |
| System Gates | 36000 gates | 24000 gates |
| Logic Cells | 912 cells | — |
| User I/O | 72 | — |
| Technology | 0.45 um antifuse | — |
| Core Architecture Voltage | 5.0 V | — |
| I/O Voltage Support | 3.3 V / 5.0 V mixed | — |
| Speed Grade | -2 | -2 |
| Programmability | One-Time Programmable (antifuse) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | 84-PLCC (J-Lead) | 84-LCC (J-Lead) PLCC-84 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration | No external boot device required | — |
| Dedicated Decode Blocks | D-modules (wide-input AND, CPLD-like) | — |
| Tindminan RoHS | Lead Free (per Kynix listing) | Lead Free |
| Packaging | Tray | — |
| Primary Applications | ASIC alternative, legacy PLD integration | — |
| Configurable Logic Blocks (CLBs) | — | 608 |
| Number of I/O | — | 72 |
| Maksimum na Taktiko ng Oras | — | 117 MHz |
| Process Technology | — | 0.45 um CMOS |
| Volte ng Pagbibigay | — | 3.3 V / 5 V |
| JESD-30 Code | — | S-PQCC-J84 |
| Programmable Type | — | In-System Programmable |
| JTAG Support | — | IEEE 1149.1 (family members 42MX24/42MX36) |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |