ADS6422IRGC25 vs ADS62P48IRGC25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ADS6422IRGC25 sa pamamagitan ng Texas Instruments at ADS62P48IRGC25 sa pamamagitan ng Texas Instruments. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Texas Instruments
ADS6422IRGC25 - Quad 12-Bit 65MSPS Serial LVDS ADC | Texas Instruments
ADS6422IRGC25 ✓ NakahandaTexas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ADS6422IRGC25 | ADS62P48IRGC25 |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 12 bits | 14 bit |
| Number of Channels | 4 (quad) | 2 (Dual) |
| Sample Rate | 65 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential | Differential analog inputs |
| Output Interface | Serialized LVDS (1-wire or 2-wire) | DDR LVDS / Parallel CMOS (selectable) |
| Volte ng Pagbibigay | 3.3 V | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Packhaging | 64-pin VQFN (RGC) 9x9 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | 3 (168 hours) | 3 |
| Tindminan RoHS | Compliant | Compliant |
| Family | ADS642x (ADS6424 105MSPS / ADS6423 80MSPS / ADS6422 65MSPS) | — |
| Coarse Gain Option | 3.5 dB programmable | — |
| Internal Reference | Yes | — |
| Lead-Free | Yes | — |
| Sample Rate (max) | — | 210 MSPS |
| Analog Supply Voltage | — | 1.8 V |
| Digital Supply Voltage | — | 3.3 V |
| Hanay ng Temperature na Operasyon | — | -40 C to +85 C (Industrial) |
| Packhaging / Kaso | — | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| Bilang ng Pin | — | 64 |
| Lead Free | — | Yes |
| Input Clock Type | — | LVDS differential clock |
| Internal Dither | — | Yes (programmable) |
| Programmable Gain | — | Yes (improves SFDR at lower FS inputs) |