CDK2308DILP64 vs CDK2308AILP64 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng CDK2308DILP64 sa pamamagitan ng MaxLinear at CDK2308AILP64 sa pamamagitan ng MaxLinear. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | CDK2308DILP64 | CDK2308AILP64 |
|---|---|---|
| Brand | MaxLinear | MaxLinear |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 10 bit | 10 bit |
| Number of Channels | 2 (Dual) | 2 (Dual) |
| Sampling Rate (max) | 80 MSPS | — |
| Supported Sample Rates | 20 / 40 / 65 / 80 MSPS (programmable) | — |
| Architecture | Pipelined ADC | Pipelined |
| Input Type | Single-ended analog | Differential / Single-ended analog |
| Power Dissipation | 78 mW per channel at 80 MSPS | [DATA_NEEDED: power in mW] |
| Supply Voltage (AVDD) | [DATA_NEEDED: AVDD nominal voltage] | — |
| Supply Voltage (DRVDD) | [DATA_NEEDED: DRVDD nominal voltage] | — |
| Input Bandwidth | [DATA_NEEDED: -3 dB input bandwidth] | [DATA_NEEDED: input bandwidth MHz] |
| SNR | [DATA_NEEDED: SNR at full scale] | [DATA_NEEDED: SNR dBFS] |
| SFDR | [DATA_NEEDED: SFDR] | — |
| ENOB | [DATA_NEEDED: effective number of bits] | — |
| Packhaging | 64-QFN (9x9 mm) | 64-pin QFN (LP) 9x9 mm with exposed pad |
| Hanay ng Temperature na Operasyon | -40 C to +85 C | -40C to +85C (industrial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Tindminan RoHS | Compliant | Compliant (per distributor listings) |
| Power-Down Modes | Per-channel standby, chip standby, full power-down | — |
| Track-and-Hold Amplifier | Integrated, optimized for IF frequencies | — |
| Manufacturer | — | Exar (MaxLinear) |
| Part Number | — | CDK2308AILP64 |
| Sampling Rate (Grade ILP64) | — | 20 MSPS |
| Family Maximum Sampling Rate | — | 80 MSPS (per family datasheet) |
| Analog Supply Voltage | — | +3.3 V |
| Digital Supply Voltage | — | +3.3 V |
| Data Interface | — | Parallel CMOS / TTL |
| Internal Reference | — | Yes (bandgap) |
| INL (Integral Non-Linearity) | — | [DATA_NEEDED: INL in LSB] |
| DNL (Differential Non-Linearity) | — | [DATA_NEEDED: DNL in LSB] |