CDK8307CILP64 vs CDK8307BILP64 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng CDK8307CILP64 sa pamamagitan ng MaxLinear at CDK8307BILP64 sa pamamagitan ng MaxLinear. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
MaxLinear
CDK8307CILP64 - 12/13-bit 65MSPS Octal ADC, LVDS Output | MaxLinear
CDK8307CILP64 ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | CDK8307CILP64 | CDK8307BILP64 |
|---|---|---|
| Brand | MaxLinear | MaxLinear |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 12/13-bit (selectable) | 12-bit or 13-bit (programmable) |
| Sample Rate | 65 MSPS maximum (20/40/50/65 MSPS grades) | — |
| Number of Channels | 8 (simultaneous sampling) | 8 |
| Digital Output Interface | Serial LVDS | — |
| Input Type | Differential analog inputs | Differential analog inputs (one per channel) |
| Reference | Internal (integrated bandgap) | Internal (integrated bandgap reference) |
| Control Interface | SPI-compatible serial | Serial control interface |
| Packhaging | 64-pin LQFP (LP64) | 64-pin QFN (LP suffix) |
| Architecture | Proprietary pipeline ADC | — |
| Power Profile | Ultra-low power (per-channel) | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Supply Voltage (AVDD) | [DATA_NEEDED: AVDD nominal] | — |
| Supply Voltage (DRVDD/LVDS) | [DATA_NEEDED: DRVDD nominal] | — |
| ENOB | [DATA_NEEDED: effective number of bits] | — |
| SNR | [DATA_NEEDED: signal-to-noise ratio] | — |
| SFDR | [DATA_NEEDED: spurious-free dynamic range] | — |
| Tindminan RoHS | Compliant (per MaxLinear product page) | Compliant |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Product Type | — | Octal Analog-to-Digital Converter (ADC) |
| Sample Rate (per channel) | — | 20 / 40 / 50 / 65 MSPS |
| Total Power Dissipation | — | 280 mW |
| Data Output Interface | — | Serial LVDS |
| Clock Architecture | — | External reference clock with integrated PLL (x12 or x14 multiplication) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: supply voltage rating] |