EP1810GC-35AB vs EP1810GI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GC-35AB sa pamamagitan ng Altera at EP1810GI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GC-35AB | EP1810GI-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Technology | CMOS EPROM | CMOS |
| Number of Macrocells | 48 | — |
| Number of Usable Gates | 1200 | — |
| Maximum Inputs | 64 | — |
| Maximum Outputs | 48 | — |
| Number of I/O Pins | 48 | — |
| Dedicated Input Pins | 12 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Package Type | Pin Grid Array (PGA), ceramic | Ceramic Pin Grid Array with UV window |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming Method | UV-erasable EPROM, in-system via JTAG-like interface | — |
| Tindminan RoHS | unknown | Non-compliant (ceramic PGA) |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 24 |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| Bilang ng Pin | — | 68 |
| Uri ng Pagpapasok | — | Through-Hole |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |