EP1810GM883B vs EP1810JI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GM883B sa pamamagitan ng Altera at EP1810JI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GM883B | EP1810JI-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | EP1810 (Classic EPLD) | — |
| Macrocells | 48 | — |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | 50 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Temperature na Operasyon | -55 °C to +125 °C (Military, MIL-STD-883B) | -40 °C to +85 °C |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | UV-erase (windowed) / OTP via JEDEC |
| Uri ng Pagpapasok | Through-hole (PGA socket or PCB through-hole) | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Manufacturer | — | Altera (now Intel FPGA) |
| Series | — | Classic EPLD Family |
| Device Type | — | UV-Erasable / OTP Complex PLD |
| Macrocell Count | — | 48 |
| Maximum Operating Frequency | — | 33.3 MHz |
| Configurable I/O Lines | — | 48 |
| Package Code | — | QCCJ |
| Terminal Form | — | J BEND |
| Package Shape | — | SQUARE |
| Number of Terminals | — | 68 |
| Temperature Grade | — | INDUSTRIAL |
| Volte ng Pagbibigay | — | 5 V (TTL compatible) |