EP1810JC-25 vs EP1810GI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-25 sa pamamagitan ng Intel at EP1810GI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-25 | EP1810GI-45 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EPLD |
| Macrocells | 48 | 24 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | -40 °C to 85 °C (industrial, per distributor listings) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | CMOS |
| Packhaging | 28-pin ceramic DIP (J) with quartz window | — |
| Uri ng Pagpapasok | Through-hole | Through-Hole |
| Erasure Method | UV light (windowed package) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (ceramic PGA) |
| Katayuan ng Lifecycle | NRND (Not Recommended for New Designs) | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Flip-Flops | — | 48 |
| Propagation Delay (tpd) | — | 45 ns |
| Speed Grade | — | -45 |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Bilang ng Pin | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Lead-Free | — | No |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |