EP1810JC-25 vs EP1810LC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-25 sa pamamagitan ng Intel at EP1810LC-45 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoletePagsanggunian na paghahambing
| Parametro | EP1810JC-25 | EP1810LC-45 |
|---|---|---|
| Brand | Intel | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EPLD |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Temperature na Operasyon | -40 °C to 85 °C (industrial, per distributor listings) | 0 °C to +70 °C (commercial) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | — |
| Packhaging | 28-pin ceramic DIP (J) with quartz window | 68-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Through-hole | Surface Mount (PLCC socket compatible) |
| Erasure Method | UV light (windowed package) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Katayuan ng Lifecycle | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |