EP1810JC-25 vs EP1810LC-45 比較
詳細並排比較 EP1810JC-25 由 Intel 與 EP1810LC-45 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 Obsolete規格比較
| 參數 | EP1810JC-25 | EP1810LC-45 |
|---|---|---|
| 品牌 | Intel | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera/Intel Classic EPLD (EP1810 series) | Altera Classic EPLD |
| Macrocells | 48 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fMAX] | — |
| Input Lines | 60 (including I/O) | — |
| I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| External Clock Inputs | 4 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | -40 °C to 85 °C (industrial, per distributor listings) | 0 °C to +70 °C (commercial) |
| Technology | CMOS, UV-erasable (windowed ceramic DIP) | — |
| 封裝 | 28-pin ceramic DIP (J) with quartz window | 68-pin PLCC (J-lead) |
| 安裝類型 | Through-hole | Surface Mount (PLCC socket compatible) |
| Erasure Method | UV light (windowed package) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| 生命週期狀態 | NRND (Not Recommended for New Designs) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |