EP1810JC-45 vs EP1810JC35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JC-45 sa pamamagitan ng Altera at EP1810JC35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JC-45 | EP1810JC35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | UV-erasable / OTP Complex PLD (EPLD) |
| Family | EP1810 (Classic EPLD Family) | Altera Classic EPLD |
| Macrocells | 48 | 48 |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Maksimum na Taktiko ng Oras | 33.3 MHz | 40 MHz |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | — |
| Packhaging | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | PLCC-68 (J-lead, ceramic) |
| Bilang ng Pin | 68 | — |
| Package Code | QCCJ | QCCJ |
| Temperature Grade | Commercial | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| Propagation Delay (tPD) | — | 35 ns |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| Temperature na Operasyon | — | 0 C to +70 C (Commercial) |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |