EP1810JI-45 vs EP1810LC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-45 sa pamamagitan ng Altera at EP1810LC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-45 | EP1810LC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | 50 MHz |
| Propagation Delay (tPD) | 50 ns | 20 ns |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| Technology | CMOS EPROM | CMOS EPROM |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| Temperature na Operasyon | -40 °C to +85 °C | 0C to +70C (commercial) |
| Volte ng Pagbibigay | 5 V (TTL compatible) | 5 V (4.75 V to 5.25 V) |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Family | — | Classic EPLD |
| Usable Gates | — | 900 |
| Macrocells | — | 48 |
| Programmability | — | UV-Erasable / OTP |
| Packhaging | — | 68-pin PLCC |
| Package Suffix | — | LC (PLCC, windowed for UV erase on L variant) |
| Speed Grade | — | 20 ns (commercial) |
| Uri ng Pagpapasok | — | Surface Mount |
| Tindminan RoHS | — | [DATA_NEEDED: rohs status] |