EP1810LC-30 vs EP1810LC-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-30 sa pamamagitan ng Altera at EP1810LC-45 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-45 - 900-Gate Classic EPLD, 48 Macro Cells, PLCC-68 | Intel
EP1810LC-45 ObsoletePagsanggunian na paghahambing
| Parametro | EP1810LC-30 | EP1810LC-45 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 48 | — |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | — |
| Packhaging | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC (J-lead) |
| Programming | Device programmer or JTAG | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0 °C to +70 °C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Bilang ng Pins | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Tindminan RoHS | unknown (legacy ceramic package) | [DATA_NEEDED: RoHS status of Rochester-sourced part] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| Logic Array Blocks | — | 4 |
| Propagation Delay (tpd) | — | 45 ns |
| Maximum Operating Frequency | — | 22.2 MHz |
| Supply Voltage (Vcc) | — | 5 V (±5%) |
| Process Technology | — | 5 V CMOS EPROM |
| Uri ng Pagpapasok | — | Surface Mount (PLCC socket compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |