EP1810LC-35 vs EP1810GI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35 sa pamamagitan ng Rochester Electronics at EP1810GI-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP1810LC-35 | EP1810GI-45 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 24 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | 45 ns |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS |
| Packhaging | 68-pin PLCC (J-Lead) | — |
| Uri ng Pagpapasok | Surface Mount (socketable) | Through-Hole |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Tindminan RoHS | [DATA_NEEDED] | Non-compliant (ceramic PGA) |
| Lead-Free | [DATA_NEEDED] | No |
| Family | — | Altera Classic EPLD |
| Flip-Flops | — | 48 |
| Speed Grade | — | -45 |
| Package Type | — | Ceramic Pin Grid Array with UV window |
| Bilang ng Pin | — | 68 |
| Programmable | — | Yes (UV-erasable, electrically programmable) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |