EP1810LC-35 vs EP1810LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35 sa pamamagitan ng Rochester Electronics at EP1810LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1810LC-35 | EP1810LI-35 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM configuration cell |
| Packhaging | 68-pin PLCC (J-Lead) | 68-pin PLCC (J-Lead, plastic) |
| Uri ng Pagpapasok | Surface Mount (socketable) | Surface Mount (PLCC socket compatible) |
| Temperature na Operasyon | 0C to +70C (commercial) | -40 C to +85 C (industrial, 'I' suffix) |
| I/O Pins | [DATA_NEEDED: I/O count exact] | — |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | — |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Tindminan RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED] | [DATA_NEEDED: lead-free status] |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | 35 (slowest in EP1810L family) |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Volte ng Pagbibigay | — | 5 V (TTL-compatible I/O) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |