EP1810LC-35T vs EP1810LC-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-35T sa pamamagitan ng Intel at EP1810LC-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-35T | EP1810LC-20T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 900 | 900 gates |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| Packhaging | 68-pin PLCC (Plastic Leaded Chip Carrier) | — |
| Package Suffix | T = Tape and Reel | — |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or direct solder) | Surface Mount (socket-compatible) |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| Tindminan RoHS | Non-compliant (legacy PLCC product) | Non-compliant (legacy 5V PLCC) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | PLCC-68 (J-lead) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |