EP1C3T100I7 vs EP1C3T100C8 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1C3T100I7 sa pamamagitan ng Intel at EP1C3T100C8 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1C3T100I7 | EP1C3T100C8 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Tapus ng Buhay |
| Series | Cyclone I | — |
| Family | Cyclone FPGA Family | Cyclone I |
| Logic Elements | 2910 LE | 2,910 LEs |
| Number of LABs/CLBs | 291 LAB | — |
| Total RAM Bits | 59904 bit | 59,904 bits |
| Number of I/O | 65 I/O | — |
| Number of Gates | [DATA_NEEDED: gate count] | — |
| Supply Voltage Core | 1.5 V | — |
| Process Technology | 130 nm | — |
| Maximum Operating Frequency | 320.1 MHz | — |
| Number of PLLs | 1 | — |
| Packhaging | 100-TQFP | TQFP-100 (14x14 mm) |
| Temperature na Operasyon | -40C to +100C (Industrial) | 0C to +85C (commercial) |
| Speed Grade | 7 | -8 (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead Pitch | [DATA_NEEDED: lead pitch] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Core Process | — | 0.13 µm SRAM |
| Core Voltage (VCCINT) | — | 1.5 V |
| M4K RAM Blocks | — | 13 (4 Kbit each) |
| Embedded Multipliers | — | Not present on EP1C3 |
| PLLs | — | 1 general-purpose PLL |
| Global Clock Networks | — | 8 |
| User I/O Pins | — | 65 |
| Configuration Modes | — | AS, PS, JTAG |
| I/O Standards | — | LVTTL, LVCMOS, SSTL-2/3, LVDS, RSDS |
| Lifecycle | — | EOL per PDN1810 (since 2019) |