EP1C6T144C8N vs EP1C6T14417N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1C6T144C8N sa pamamagitan ng Intel at EP1C6T14417N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1C6T144C8N | EP1C6T14417N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Series | Cyclone® | — |
| Family | Cyclone I | Cyclone |
| Logic Elements (LE) | 5,980 | — |
| Logic Array Blocks (LAB) | 598 | — |
| Total RAM Bits | 92,160 | 92,160 |
| User I/O Pins | 98 | — |
| Number of I/O Banks | 4 | — |
| PLLs | 2 | 2 |
| Maximum Internal Frequency | 275 MHz | — |
| Speed Grade | C8 (commercial) | 7 (-7) |
| Core Voltage (VCCINT) | 1.425 V to 1.575 V (typ. 1.5 V) | 1.5 V (typical) |
| Process Technology | 0.13 µm all-layer copper SRAM | 130 nm TSMC |
| Packhaging | 144-pin TQFP | TQFP-144 (1.0 mm pitch) |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | 0°C to +85°C (commercial) | 0C to +85C (commercial) |
| Configuration Method | Active Serial (EPCS), Passive Serial, JTAG | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | Compliant | Compliant |
| Logic Elements | — | 5,980 |
| Embedded M4K RAM Blocks | — | 20 |
| Maximum User I/O Pins | — | 185 |
| Global Clock Networks | — | 20 |
| LVDS Channels | — | 34 differential pairs (max) |
| I/O Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (bank-dependent) |
| Configuration Mode | — | Active Serial (AS) / Passive Serial (PS) / JTAG |