EP1K100QC208-3N vs EP1K100QC208-3 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K100QC208-3N sa pamamagitan ng Altera at EP1K100QC208-3 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP1K100QC208-3N EP1K100QC208-3N - ACEX-1K FPGA 100K Gates | Altera

EP1K100QC208-3N - ACEX-1K FPGA 100K Gates | Altera

EP1K100QC208-3N Obsolete

Pagsanggunian na paghahambing

Parametro EP1K100QC208-3N EP1K100QC208-3
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Product Series ACEX-1K —
Device Type Field Programmable Gate Array (FPGA) FPGA (Field Programmable Gate Array)
Number of Logic Elements 4992 4,992
Number of LABs 624 —
Embedded RAM Bits 49152 —
Total Typical Gates 100K —
Number of User I/Os 147 —
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage Range [DATA_NEEDED: I/O supply voltage range] —
Maximum Internal Clock Frequency 200 MHz 200 MHz
Package Type 208-BFQFP 208-Pin BFQFP (PQFP)
Bilang ng Pins 208 —
Uri ng Pagpapasok Surface Mount Surface Mount
Terminal Form Gull Wing Gull Wing
JTAG Boundary Scan IEEE Std. 1149.1-1990 compliant built-in BST —
Lead-Free Version Yes (N suffix) —
Hanay ng Temperature na Operasyon Commercial grade ([DATA_NEEDED: exact operating temperature range]) —
Supported Configuration Devices EPC2/EPC16 family ([DATA_NEEDED: exact ACEX-1K supported list]) —
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS certificate status] —
Product Family — ACEX 1K
Process Technology — 0.22 um CMOS
Typical Gate Count — 100,000 gates
Logic Array Blocks (LABs) — 624
Total RAM Bits — 49,152 bits
Maximum User I/O — 147
Number of Terminals — 208
Package Shape — Square
Temperature Grade — Commercial
Speed Grade — -3
RoHS / Lead-Free Suffix — No -N suffix; compliance not verified in retrieved source data
I/O Standards Supported — [DATA_NEEDED: supported I/O standards]
Configuration Memory — SRAM-based loadable PLD

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