EP1K10TC100-2N vs EP1K10TC100-3N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K10TC100-2N sa pamamagitan ng Altera at EP1K10TC100-3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EP1K10TC100-2N EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera

EP1K10TC100-2N - ACEX-1K FPGA, 10K Gates, 576 Cells | Altera

EP1K10TC100-2N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP1K10TC100-2N EP1K10TC100-3N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family ACEX-1K ACEX 1K
Logic Elements / Cells 576 —
Typical Gates 10,000 —
Logic Array Blocks (LABs) 72 —
Embedded Memory (EAB) 12,288 bits 12,288 bits
Maximum User I/O 66 —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Core Voltage (VCCINT) 2.5 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5 V —
Speed Grade -2 -3 (commercial)
Maximum Frequency 200 MHz —
Packhaging 100-pin TQFP (1.0 mm body, 0.5 mm pitch) 100-pin TQFP
Temperature na Operasyon 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature range]
Configuration Modes Passive Serial, Active Serial, JTAG —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS Lead-free / RoHS compliant [DATA_NEEDED: RoHS compliance]
Series — ACEX-1K
Manufacturer — Intel (formerly Altera)
Typical Gate Count — 10,000 gates
Logic Elements (Cells) — 576
Number of LABs — 72
User I/O Count — 66
Operating Voltage (Core) — 2.5 V
Maximum Internal Clock Frequency — 200 MHz
JTAG Support — Yes (IEEE 1149.1-1990)
PCI Compliance — PCI Local Bus Specification Revision 2.2 (5.0 V)
Configuration — JTAG / serial configuration device

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