EP1K50FC256-1N vs EP1K50FC256-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K50FC256-1N sa pamamagitan ng Intel at EP1K50FC256-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1K50FC256-1N EP1K50FC256-2
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family ACEX-1K ACEX 1K Family
Series ACEX-1K (2.5 V) ACEX-1K
Maximum Logic Elements 2,880 —
Logic Array Blocks (LABs) 360 —
Typical Gates 50,000 50,000
Maximum System Gates 199,000 —
Embedded Memory (EAB) Bits 40,960 bits —
User I/O Pins 186 —
Core Supply Voltage 2.5 V (2.375 V to 2.625 V) —
Maximum Internal Frequency 250 MHz —
Process Technology 0.22 um CMOS 0.22 µm CMOS
Typical Operating Current 5 mA —
Speed Grade -1 (commercial) —
Temperature na Operasyon 0 C to 70 C (commercial) 0°C to +70°C (commercial)
Packhaging 256-ball FBGA (FineLine BGA) —
Uri ng Pagpapasok Surface Mount Surface Mount
Lead Status Lead-free (-N suffix) —
Tindminan RoHS Compliant Compliant
Programmable I/O Standards LVTTL, LVCMOS, PCI, GTL+ —
Configuration Method SRAM-based, JTAG (IEEE 1149.1) SRAM-based, volatile configuration
Logic Cells / Elements — 2,880
Number of LABs/CLBs — 360
User I/Os — 186
Total RAM Bits — 40,960
Number of Gates — 50,000
Voltage - Supply — 2.375 V to 2.625 V (nominal 2.5 V)
Propagation Delay — 0.4 ns (per Partstack listing)
Packhaging / Kaso — 256-BGA (FineLine BGA, 17x17 mm)
Style ng Pagpapasok — SMD/SMT
Programming Type — In-System Programmable via JTAG (IEEE 1149.1)
REACH Status — Compliant
Level ng MSL — [DATA_NEEDED: MSL level]

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