EP1K50QC208-3N vs EP1K50QC208-2N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1K50QC208-3N sa pamamagitan ng Altera at EP1K50QC208-2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1K50QC208-3N EP1K50QC208-2N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family ACEX-1K ACEX 1K
Typical Gates 50,000 50,000
Logic Elements (LEs) 2,880 —
Logic Array Blocks (LABs) 360 360
Embedded RAM 40,960 bits (10 EABs × 4,096 bits) —
Maximum User I/Os 147 —
Maximum Operating Frequency 166.67 MHz —
Pin-to-Pin Logic Delay 0.5 ns (typical, -3 speed grade) —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage (VCCINT) 2.5 V —
I/O Supply Voltage (VCCIO) 3.3 V (PCI-compatible I/O banks) —
Packhaging 208-pin PQFP / BFQFP (Plastic Quad Flat Pack) 208-pin PQFP (BFQFP)
Uri ng Pagpapasok Surface Mount Surface Mount (Gull-Wing)
Temperature na Operasyon 0 °C to +70 °C (Commercial) 0 °C to 85 °C (Commercial)
Programming Interface IEEE 1149.1 JTAG + in-system configurable —
Lead-Free / RoHS Compliant (Pb-free terminal finish per 'N' suffix) —
Series — ACEX-1K
Logic Elements — 2,880
Embedded Memory (EAB SRAM) — 40 kbit
User I/Os — 147
Number of I/O Banks — [DATA_NEEDED: number of I/O banks]
Maximum Toggle Frequency — 200 MHz
Pin-to-Pin Delay (LE) — 0.4 ns (per data sheet snippet)
Core Supply Voltage — 2.5 V
I/O Supply Voltage — [DATA_NEEDED: I/O supply voltage]
Configuration Interface — JTAG (IEEE 1149.1), Serial (PS/AS)
Level ng MSL — [DATA_NEEDED: MSL level]
Tindminan RoHS — [DATA_NEEDED: RoHS status]

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