EP1M120F484C7N vs EP1M120F484C6N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1M120F484C7N sa pamamagitan ng Altera at EP1M120F484C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1M120F484C7N EP1M120F484C6N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Mercury Mercury (APEX PLD platform)
System Gates 120,000 —
Logic Elements / Cells 4,800 —
Logic Array Blocks (LABs) 480 480
Embedded Memory (RAM bits) 49,152 —
Maximum User I/O Pins 303 —
Logic Family CMOS —
Core Supply Voltage 1.8 V —
Integrated Transceivers Yes - CDR to 1.25 Gbps —
Package Type 484-ball FineLine BGA (FCBGA) —
Package Code F484 —
Temperature na Operasyon 0°C to 85°C (Commercial) 0C to 85C (commercial)
Temperature Grade Suffix C (Commercial, 0–85°C) —
Speed Grade 7 —
RoHS / Lead-Free Suffix N (lead-free) —
Process Node [DATA_NEEDED: process node] —
Transceiver Channels [DATA_NEEDED: number of transceiver channels] —
Typical Gates — 120,000
Logic Cells / Elements — 4,800
User I/Os — 303
Packhaging — 484-ball FC-FBGA (FineLine BGA)
Core Supply Voltage (VCCINT) — 1.71 V to 1.89 V (1.8 V nominal)
Transceiver Data Rate — Up to 1.25 Gbps with CDR
Process Technology — CMOS
Architecture — LUT-based, optimized for high-speed interconnect
MultiCore Support — Yes (hot socketing)
Uri ng Pagpapasok — Surface Mount
Level ng MSL — 3 (per JEDEC J-STD-020)
Tindminan RoHS — Compliant

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