EP1S10B672C6 vs EP1S10F672C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10B672C6 sa pamamagitan ng Intel at EP1S10F672C6 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10B672C6 | EP1S10F672C6 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Manufacturer | Intel / Altera | — |
| Series | Stratix | Stratix® I |
| Logic Elements / Cells | 10,570 | — |
| LABs / CLBs | 1,057 | — |
| User I/Os | 345 | — |
| Packhaging | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | 672-ball FineLine BGA (FBGA) |
| Supply Voltage (Core) | 1.5 V (1.425 V - 1.575 V) | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Operating Frequency | 450.05 MHz | — |
| Temperature na Operasyon | 0 C to 85 C (Commercial Extended) | 0C to +85C (Commercial) |
| Logic Family | CMOS | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Supplier Device Package | 672-BGA | — |
| Memory | Embedded TriMatrix (MRAM/M4K) blocks | — |
| DSP Blocks | Yes, dedicated multiply-accumulate blocks | 6 |
| Clock Management | PLLs for clock synthesis | — |
| Configuration | JTAG / passive serial / fast passive parallel | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Family | — | Stratix FPGA |
| Logic Elements (LE) | — | 10,570 |
| Logic Array Blocks (LABs) | — | 1057 |
| Total Memory Bits | — | 920,448 bits |
| Embedded Memory | — | TriMatrix (MRAM/M4K) |
| Number of I/Os | — | 345 |
| Number of PLLs | — | 12 (6 per device side) |
| Core Voltage | — | 1.5 V |
| Maximum Core Frequency | — | 420.17 MHz |
| Configuration Modes | — | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |