EP1S10B672C6 vs EP1S10F672C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10B672C6 sa pamamagitan ng Intel at EP1S10F672C7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10B672C6 | EP1S10F672C7N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Intel / Altera | — |
| Series | Stratix | Stratix |
| Logic Elements / Cells | 10,570 | 10,570 |
| LABs / CLBs | 1,057 | — |
| User I/Os | 345 | — |
| Packhaging | 672-BBGA (35 x 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core) | 1.5 V (1.425 V - 1.575 V) | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Operating Frequency | 450.05 MHz | 420.17 MHz |
| Temperature na Operasyon | 0 C to 85 C (Commercial Extended) | 0C to +85C (Commercial) |
| Logic Family | CMOS | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Supplier Device Package | 672-BGA | — |
| Memory | Embedded TriMatrix (MRAM/M4K) blocks | — |
| DSP Blocks | Yes, dedicated multiply-accumulate blocks | 6 |
| Clock Management | PLLs for clock synthesis | — |
| Configuration | JTAG / passive serial / fast passive parallel | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance] |
| Number of LABs/CLBs | — | 1,057 |
| Total RAM Bits | — | 920,448 |
| Number of User I/Os | — | 345 |
| Number of Gates | — | [DATA_NEEDED: total gate count] |
| Package Type | — | 672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch |
| Core Voltage | — | 1.5 V |
| Configuration Method | — | SRAM, JTAG, passive/active serial/parallel |
| Level ng MSL | — | [DATA_NEEDED: MSL moisture sensitivity level] |