EP1S10F484C6N vs EP1S10F484C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F484C6N sa pamamagitan ng Intel at EP1S10F484C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10F484C6N | EP1S10F484C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix | Stratix (EP1S) |
| Logic Elements / Cells | 10,570 | — |
| Number of LABs / CLBs | 1,057 | — |
| Total RAM Bits | 920,448 | — |
| Number of User I/O | 335 | — |
| Packhaging | 484-FBGA (23 × 23 mm, 1.0 mm pitch) | 484-ball FineLine BGA (FBGA-484), 23 x 23 mm, 1 mm pitch |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Supply Voltage - Operating | 1.425 V to 1.575 V (core 1.5 V) | — |
| Speed Grade | C6 | C7 (-7) |
| Temperature na Operasyon | 0 °C to 85 °C (TJ) | — |
| Uri ng Pagpapasok | Surface Mount (SMT) | — |
| Lead Free | Yes | — |
| Configuration Method | SRAM - volatile (JTAG / passive serial / passive parallel / fast passive parallel) | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL, LVDS | — |
| On-chip Resources | TriMatrix memory (M512, M4K, M-RAM), DSP blocks, PLLs | — |
| Manufacturer | — | Intel (formerly Altera) |
| Core Voltage | — | 1.5 V |
| Logic Elements | — | 10,570 |
| Logic Array Blocks (LABs) | — | 1,057 |
| Embedded Memory (Total) | — | 920,448 bits |
| Embedded Memory Blocks | — | TriMatrix (M512/M4K/M-RAM) |
| Embedded DSP Blocks | — | 48 |
| Maximum User I/O | — | 335 |
| PLLs | — | 12 |
| Operating Temperature (Commercial) | — | 0 C to +85 C |
| Configuration Methods | — | JTAG, Passive Serial, Passive Parallel |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |