EP1S10F484I6N vs EP1S10F484C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F484I6N sa pamamagitan ng Intel at EP1S10F484C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S10F484I6N - Stratix 10,570 LEs FPGA 484-FBGA | Intel (Altera)
EP1S10F484I6N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S10F484I6N | EP1S10F484C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | Stratix | Stratix (original) |
| Logic Elements | 10,570 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| Logic Array Blocks (LABs) | 1,057 | 1,057 |
| Embedded Memory (Bits) | 920,448 | — |
| DSP Blocks | 48 | — |
| Maximum User I/O | 335 | 335 |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Voltage (VCCINT) | 1.5 V | 1.5 V |
| Number of PLLs | 6 | — |
| Temperature na Operasyon | 0C to +85C (Industrial) | — |
| Packhaging | 484-ball FBGA (FCBGA), 23 x 23 mm, 1 mm pitch | 484-ball FCBGA (F484), 23 x 23 mm, 1.0 mm pitch |
| Uri ng Pagpapasok | Surface Mount (Flip-Chip BGA) | Surface Mount |
| Peak Reflow Temperature | 245 C | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Active Serial | — |
| Internal Core Speed | up to 450 MHz | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Logic Family | CMOS | — |
| Terminal Finish | Tin-Silver-Copper (SnAgCu) | — |
| Series | — | Stratix |
| Logic Elements (LEs) | — | 10,570 |
| Embedded Memory Bits | — | 920,448 |
| TriMatrix Memory Blocks | — | 14 |
| Embedded DSP Blocks | — | 6 (≈48 9-bit multipliers) |
| PLLs | — | 4 |
| Global Clock Networks | — | 12 |
| User I/O Standard Support | — | LVDS, LVPECL, PCI-X, RapidIO, DDR |
| Maximum Internal Frequency | — | 500 MHz (per Stratix datasheet) |
| Operating Temperature (TJ) | — | 0 °C to 85 °C (Commercial) |
| Configuration Method | — | JTAG / Passive Serial / Active Serial |
| Device Status | — | Obsolete - last time buy completed |
| Design Toolchain | — | Quartus II (≤ v13.0) |