EP1S10F672C7 vs EP1S10B672C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F672C7 sa pamamagitan ng Altera at EP1S10B672C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10F672C7 | EP1S10B672C7 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | Stratix | — |
| Logic Elements | 10,570 | 10,570 |
| Embedded Memory | 920,448 bits | — |
| User I/Os | 345 | — |
| Packhaging | 672-pin FBGA (FineLine BGA) | — |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | 35 x 35 mm |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Logic Cells | 10,570 | — |
| LABs (Logic Array Blocks) | 1,057 | — |
| Temperature na Operasyon | 0 C to 85 C (Commercial) | 0 °C to 85 °C (Commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| I/O Standards | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| Configuration Mode | JTAG, Passive Serial, Active Serial | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | Stratix |
| Embedded Memory (Total) | — | 920 Kbits |
| DSP Blocks | — | Yes (DSP multiplier blocks) |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Supply Voltage (Core) | — | 1.5 V |
| Package Type | — | 672-ball FineLine BGA |
| Ball Pitch | — | 1.27 mm |
| Logic Family | — | CMOS |
| Temperature Grade | — | Commercial (C) |
| Speed Grade | — | 7 |
| Configuration Method | — | JTAG / EPC serial configuration |