EP1S10F672C7 vs EP1S10F672C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F672C7 sa pamamagitan ng Altera at EP1S10F672C6 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10F672C7 | EP1S10F672C6 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | Stratix | Stratix FPGA |
| Logic Elements | 10,570 | — |
| Embedded Memory | 920,448 bits | TriMatrix (MRAM/M4K) |
| User I/Os | 345 | — |
| Packhaging | 672-pin FBGA (FineLine BGA) | 672-ball FineLine BGA (FBGA) |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Logic Cells | 10,570 | — |
| LABs (Logic Array Blocks) | 1,057 | — |
| Temperature na Operasyon | 0 C to 85 C (Commercial) | 0C to +85C (Commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| I/O Standards | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| Configuration Mode | JTAG, Passive Serial, Active Serial | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Series | — | Stratix® I |
| Logic Elements (LE) | — | 10,570 |
| Logic Array Blocks (LABs) | — | 1057 |
| Total Memory Bits | — | 920,448 bits |
| DSP Blocks | — | 6 |
| Number of I/Os | — | 345 |
| Number of PLLs | — | 12 (6 per device side) |
| Core Voltage | — | 1.5 V |
| Maximum Core Frequency | — | 420.17 MHz |
| Configuration Modes | — | Passive Serial (PS), Fast Passive Parallel (FPP), Active Serial (AS) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |