EP1S10F672C7 vs EP1S10F672I7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F672C7 sa pamamagitan ng Altera at EP1S10F672I7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S10F672C7 | EP1S10F672I7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | Stratix | Stratix |
| Logic Elements | 10,570 | 10,570 |
| Embedded Memory | 920,448 bits | 920 Kbits (TriMatrix) |
| User I/Os | 345 | 345 |
| Packhaging | 672-pin FBGA (FineLine BGA) | 672-ball FineLine BGA, 35 x 35 mm, 1.27 mm pitch |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Logic Cells | 10,570 | — |
| LABs (Logic Array Blocks) | 1,057 | — |
| Temperature na Operasyon | 0 C to 85 C (Commercial) | 0C to 85C |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| I/O Standards | LVTTL, LVCMOS, LVDS, SSTL, HSTL | — |
| Configuration Mode | JTAG, Passive Serial, Active Serial | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: per Intel PDN] |
| Logic Array Blocks (LABs) | — | 1,057 |
| Core Supply Voltage | — | 1.5 V |
| Maximum Internal Frequency | — | 420.17 MHz |
| Logic Family | — | CMOS |
| DSP Blocks | — | Yes (dedicated) |
| Configuration Interface | — | Active Serial / Passive Serial / JTAG |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Speed Grade | — | I7 (industrial, -7 speed bin) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, typical for BGA of this era) |