EP1S10F780C5N vs EP1S10F780I6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S10F780C5N sa pamamagitan ng Intel at EP1S10F780I6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S10F780C5N - Stratix 10570 Cells FPGA, 780-FBGA | Intel (Altera)
EP1S10F780C5N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP1S10F780C5N | EP1S10F780I6N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | Stratix | Stratix |
| Logic Elements | 10570 | 10,570 |
| Total RAM Bits | 920448 | — |
| User I/O Count | 426 | — |
| Core Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to +85C (Commercial) | -40 °C to +100 °C (industrial) |
| Packhaging | 780-ball FBGA (29 x 29 mm, 1 mm pitch) | 780-ball FineLine BGA, 29 x 29 mm, 1.0 mm pitch |
| Process Technology | 130 nm CMOS | 0.13 µm CMOS |
| Internal Operating Frequency (max) | 500 MHz | — |
| Number of Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| DSP Blocks | 12 (per family datasheet) | 12 |
| PLLs | [DATA_NEEDED: PLL count] | 6 |
| Configuration Modes | Passive Serial, Active Serial, JTAG | Active Serial (AS), Passive Serial (PS), JTAG |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, LVDS (per family datasheet) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (N suffix) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | Yes | — |
| Speed Grade | C5 | -6 (6.0 ns core clock period) |
| Logic Array Blocks (LABs) | — | 1,057 |
| User I/Os | — | 426 |
| Embedded RAM (Total) | — | 920,448 bits |
| M512 Blocks | — | 94 (32 x 18 bits each) |
| M4K Blocks | — | 60 (128 x 36 bits each) |
| M-RAM Blocks | — | 1 (4 Kbit) |
| Clock Outputs | — | 16 |
| Transceiver Channels | — | 12 (not populated on I6 speed grade) |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V (per bank) |
| Level ng MSL | — | 3 (168 hours) |
| Logic Family | — | CMOS |
| Supply Voltage Nominal | — | 1.5 V |