EP1S20B672C6N vs EP1S20F672I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20B672C6N sa pamamagitan ng Intel at EP1S20F672I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S20B672C6N | EP1S20F672I7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | Stratix | Stratix (first generation) |
| Series | EP1S20 | — |
| Logic Elements (LE) | 18,460 | — |
| Logic Array Blocks (LAB) | 1,846 | — |
| Embedded Memory | 1,669,248 bits | — |
| Maximum User I/O | 426 | — |
| Process Technology | 130 nm CMOS | — |
| Core Voltage | 1.5 V | — |
| Packhaging | 672-ball BGA (672-BBGA), 35 x 35 mm, 1.27 mm pitch | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Temperature na Operasyon | 0 C to +85 C (Commercial) | -40C to +85C (industrial grade, I7 suffix) |
| Speed Grade | 6 | — |
| Configuration Method | Passive Serial / Fast Passive Parallel / JTAG | — |
| Tindminan RoHS | Compliant | unknown |
| Katayuan ng Lifecycle | Not Recommended for New Designs (NRND) | — |
| Logic Elements (LEs) | — | 18,460 |
| Maximum RAM Bits | — | 1,669,248 |
| DSP Blocks | — | [DATA_NEEDED: exact DSP block count] |
| Maximum User I/Os | — | 426 |
| Supply Voltage (VCCINT core) | — | 1.5 V |
| Logic Family | — | CMOS |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| Number of Pins / Balls | — | 672 |
| Clock Management PLLs | — | [DATA_NEEDED: PLL count] |
| Lead-Free / Finish | — | SnPb (e0 per Partstack datasheet extract) |
| Level ng MSL | — | unknown |
| Status | — | Last Time Buy (per distributor notices) |