EP1S20B672C6N vs EP1S20F672I7 比較

詳細並排比較 EP1S20B672C6N 由 Intel 與 EP1S20F672I7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EP1S20F672I7 EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera

EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera

EP1S20F672I7 ⚠ 最後購買機會

規格比較

參數 EP1S20B672C6N EP1S20F672I7
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 最後購買
Family Stratix Stratix (first generation)
Series EP1S20 —
Logic Elements (LE) 18,460 —
Logic Array Blocks (LAB) 1,846 —
Embedded Memory 1,669,248 bits —
Maximum User I/O 426 —
Process Technology 130 nm CMOS —
Core Voltage 1.5 V —
封裝 672-ball BGA (672-BBGA), 35 x 35 mm, 1.27 mm pitch 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch
安裝類型 Surface Mount Surface Mount (BGA)
工作溫度 0 C to +85 C (Commercial) -40C to +85C (industrial grade, I7 suffix)
Speed Grade 6 —
Configuration Method Passive Serial / Fast Passive Parallel / JTAG —
RoHS 狀態 Compliant unknown
生命週期狀態 Not Recommended for New Designs (NRND) —
Logic Elements (LEs) — 18,460
Maximum RAM Bits — 1,669,248
DSP Blocks — [DATA_NEEDED: exact DSP block count]
Maximum User I/Os — 426
Supply Voltage (VCCINT core) — 1.5 V
Logic Family — CMOS
Configuration Modes — Passive Serial, Passive Parallel, JTAG
Number of Pins / Balls — 672
Clock Management PLLs — [DATA_NEEDED: PLL count]
Lead-Free / Finish — SnPb (e0 per Partstack datasheet extract)
MSL 等級 — unknown
Status — Last Time Buy (per distributor notices)

資料表與資源

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