EP1S20F672C6N vs EP1S20F672I7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C6N sa pamamagitan ng Intel at EP1S20F672I7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1S20F672I7 - Stratix FPGA, 18,460 LEs, 672-BGA | Intel / Altera
EP1S20F672I7 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP1S20F672C6N | EP1S20F672I7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Huling Pagbili |
| Family | Stratix | Stratix (first generation) |
| Logic Elements | 18,460 | — |
| Total RAM Bits | 1,669,248 | — |
| User I/O Count | 426 | — |
| Packhaging | 672-BBGA (FineLine BGA) 35 x 35 mm | 672-BBGA (FineLine BGA), 35 x 35 mm, 1.27 mm pitch |
| Package Pitch | 1.27 mm | — |
| Core Voltage | 1.5 V | — |
| Logic Family | CMOS | CMOS |
| Temperature na Operasyon | 0 C to 85 C (commercial) | -40C to +85C (industrial grade, I7 suffix) |
| Speed Grade | -6 | — |
| Configuration Mode | PS, FPP, JTAG | — |
| Embedded DSP Blocks | Yes (36 x 36-bit multipliers) | — |
| TriMatrix Memory | M512, M4K, M-RAM blocks | — |
| PLLs | 12 (4 enhanced) | — |
| Global Clock Networks | 16 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Lead Free | Yes | — |
| Tindminan RoHS | Compliant | unknown |
| Logic Elements (LEs) | — | 18,460 |
| Maximum RAM Bits | — | 1,669,248 |
| DSP Blocks | — | [DATA_NEEDED: exact DSP block count] |
| Maximum User I/Os | — | 426 |
| Supply Voltage (VCCINT core) | — | 1.5 V |
| Configuration Modes | — | Passive Serial, Passive Parallel, JTAG |
| Number of Pins / Balls | — | 672 |
| Clock Management PLLs | — | [DATA_NEEDED: PLL count] |
| Lead-Free / Finish | — | SnPb (e0 per Partstack datasheet extract) |
| Level ng MSL | — | unknown |
| Status | — | Last Time Buy (per distributor notices) |